1. Field of the Invention
The present invention generally relates to the fabrication of metal oxide semiconductor field effect transistors (MOSFET) and, more particularly, to a MOSFET devices having a wrapped-gate structure.
2. Background Description
The escalating requirements for high performance and density associated with ultra large scale integration semiconductor devices require high speed and reliability and increased manufacturing throughput for competitiveness.
Integrated circuits, including transistors, are typically formed from either bulk silicon starting material, silicon on insulator (SOI) starting material, or SOI material that is formed from a bulk semiconductor starting material during processing. A gate dielectric layer, typically an oxide, is formed on the starting material (i.e., substrate) and a gate electrode, typically polysilicon, is formed on the gate dielectric layer. Source and drain regions are formed in the substrate, typically by ion implantation, and the region underlying the gate electrode serves as a channel region between the source and drain regions.
As device size shrinks, the industry has been observing new problems and challenges which have not been accompanied with the relatively larger devices with lower density. Among them, the major challenges are to achieve better gate control of the substrate potential for a steeper sub-threshold slope and a lower sensitivity to the xe2x80x9cbody to sourcexe2x80x9d voltage, to increase an effective gate width, to improve the short channel effect and to reduce the kink effect. Therefore, there has been a need for a new transistor operation scheme which provides solutions to those problems and challenges.
An object of the present invention is to provide an improved transistor structure which provides an improved gate control of the substrate potential, a steep sub-threshold slope, and low sensitivity to the xe2x80x9cbody-to-sourcexe2x80x9d voltage.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objectives are achieved in part by a semiconductor device comprising a substrate having an upper surface and first and second side surfaces substantially parallel to each other. A channel region is arranged between the first and second side surfaces within the substrate. Source and drain regions are formed in the substrate and separated by the channel region. A gate electrode is arranged on the upper surface and the first and second side surfaces of the substrate with a gate oxide therebetween.
Another aspect of the present invention is a method for manufacturing a semiconductor device comprising the step of forming a substrate having an upper surface and first and second side surfaces. Source and drain regions are formed in the substrate with a channel region therebetween. A gate oxide is formed on the upper surface and the first and second side surfaces of the substrate to cover the channel region. A gate electrode is formed on the gate oxide such that the gate electrode overlies the channel region from said upper surface and the first and second side surfaces of the substrate.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein a preferred embodiment of the present invention is shown and described. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.